##############################################################################
 #  Copyright (c) 2019, Xilinx, Inc.
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###############################################################################
###############################################################################
 #
 #  Authors: Giulio Gambardella <giuliog@xilinx.com>
 #           Mario Ruiz         <mruiznog@xilinx.com>
 #
 # \file test_dwcnm.tcl
 #
 # Tcl script for HLS csim, synthesis and cosim of the datawidth converter block
 #
###############################################################################
open_project hls-syn-dwcnm
add_files dwcnm_top.cpp -cflags "-std=c++0x -I$::env(FINN_HLS_ROOT) -I$::env(FINN_HLS_ROOT)/tb -DINPUT_WIDTH=512 -DOUT_WIDTH=48" 
add_files -tb dwcnm_tb.cpp -cflags "-std=c++0x -I$::env(FINN_HLS_ROOT) -I$::env(FINN_HLS_ROOT)/tb -DINPUT_WIDTH=512 -DOUT_WIDTH=48 -DIMAGE_SIZE=1204224" 
set_top Testbench_dwcnm
open_solution sol1
set_part {xczu3eg-sbva484-1-i}
create_clock -period 5 -name default
csim_design
csynth_design
cosim_design
exit